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2001-09-05 3/52 thncfxxxmaa series preliminar y version product specifications product specifications product specifications product specifications dimensions dimensions dimensions dimensions type i card 36.4mm(l) x 42.8mm (w) x 3.3mm (h) weight 1 4.2 g or 0.5 oz storage capacities storage capacities storage capacities storage capacities 8, 1 6, 32, 48, 64, 96, 1 28, 1 60, 1 92, 256, 320, 384 and up to 5 1 2 mb mbytes (unformatted) system compatibility system compatibility system compatibility system compatibility please refer to the compatibility list. performance performance performance performance data transfer rates: up to 4. 1 mbyte/s in ata pio mode 4 to/from flash memory: up to 1 2.5 mbytes/s to/from host: up to 20mbytes/s sustained write: up to 2.98mbyte/s in ata pio mode 4 sustained read: up to 5.62mbyte/s in ata pio mode 4 command to dreq: <4ms idle to read < 1 s idle to write < 1 s sram data buffer 6 kbytes sram operating voltage operating voltage operating voltage operating voltage 3.3v / 5v +/- 1 0% power consumption power consumption power consumption power consumption read mode 30 ma (typ) write mode 30 ma (typ) sleep mode 1 00ua (typ) environment conditions environment conditions environment conditions environment conditions operating temperature 0 to 60 storage temperature -20 to 65 relative humidity 95%(max)
2001-09-05 4/52 thncfxxxmaa series preliminar y version electrical specification electrical specification electrical specification electrical specification absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings symbol rating value unit vcc power supply voltage -0.3 to 7 v vin input voltage -0.3 to 7 v tstg storage temperature -20 to 65 topr operating temperature 0 to 60 dc recommended operating conditions dc recommended operating conditions dc recommended operating conditions dc recommended operating conditions symbol parameter min max unit vcc power supply voltage 3.0 5.5 v vih high level input voltage 2.2 vcc+0.3 v vil low level input voltage -0.3 * 0.8 v note: - 0.8v (pulse width <= 1 0ns) dc characteristics (ta = 0 dc characteristics (ta = 0 dc characteristics (ta = 0 dc characteristics (ta = 0 to 65 to 65 to 65 to 65 , vcc = 3. 1 5v to 5.5v) , vcc = 3. 1 5v to 5.5v) , vcc = 3. 1 5v to 5.5v) , vcc = 3. 1 5v to 5.5v) symbol parameter min typ max unit icco operating current 26 50 ma iccs sleep mode current 75 200 ua voh high level output voltage 2.4 v vol low level output voltage 0.4 v
2001-09-05 5/52 thncfxxxmaa series preliminar y version physical specifications type i compactflash storage card and cf+ card dimensions note: the optional notched configuration was shown in the cf specification rev.1.0. in specification rev. 1.2. the notch was removed for ease of tooling. this optional confi g uration can be used but it is not recommended. 1.01mm ? 0.7 ( .039 in ? .003) top 26 50 1 25 .99mm ? .05 (.039 in. ? . 002) 1.01mm ? 0.7 ( .039 in ? .003) 3.30mm ? .10 ( .130 in ? .004 ) 1.60mm ? .05 ( .063 in ? .002) 4xr 0.5mm ? .1 (4xr.020 in. ? . 004) 41.66mm ? .13(1.640 in. ? . 005) 42.80mm ? .10) (1.685 in. ? . 004) 0.63mm ? .07 (.025 in. ? . 003) 0.76mm ? .07 (0.30 in. ? . 003) 2x 3.00mm ? .07 (2x .118 in. ? . 003) 36.40mm ? .15 (1.433 in. ?? .006) 2.15mm ? .07 (.085 in. ? . 003) 2.44mm ? .07 (.096 in. ? . 003) 2x25.78mm ? .07 (2x1.015 in ? .003) 2x12.00mm ? .10 (2x.472 in ? .004)
2001-09-05 6/52 thncfxxxmaa series preliminar y version electrical interface electrical interface electrical interface electrical interface physical description physical description physical description physical description the host is connected to the compactflash storage card or cf+ card using a standard 50-pin connector. the connector in the host consists of two rows of 25 male contacts each on 50 mil ( 1 .27 mm) centers. pin assignments and pin type pin assignments and pin type pin assignments and pin type pin assignments and pin type the signal/pin assignments are listed in table 4. low active signals have a ? - ? prefix. pin types are input, output or input/output. section 4.3 defines the dc characteristics for all input and output type structures. electrical description electrical description electrical description electrical description the compactflash storage card functions in three basic modes: 1 ) pc card ata using i/o mode, 2) pc card ata using memory mode and 3) true ide mode, which is compatible with most disk drives. compactflash storage cards are required to support all three modes. the cf cards normally function in the first and second modes, however they can optionally function in true ide mode. the configuration of the compactflash card will be controlled using the standard pcmcia configuration registers starting at address 200h in the attribute memory space of the storage card.or for true ide mode, pin 9 being grounded. the configuration of the cf card will be controlled using configuration registers. the configuration registers are starting at the address defined in the configuration tuple (cistpl_config) in the attribute memory space of the cf card. signals whose source is the host are designated as inputs while signals that the compactflash storage card sources are outputs. the compactflash storage card logic levels conform to those specified in the pcmcia release 2. 1 specification. each signal has three possible operating modes: 1 ) pc card memory mode 2) pc card i/o mode 3) true ide mode true ide mode is required for compactflash storage cards. all outputs from the card are totem pole except the data bus signals that are bi-directional tri-state.
2001-09-05 7/52 thncfxxxmaa series preliminar y version pin assignments and pin type pc card memory mode pc card i/o mode true ide mode pin num. signal name pin type in,out type pin num. signal name pin type in,out type pin num. signal name pin type in,out type 1 gnd ground 1 gnd ground 1 gnd ground 2 d03 i/o i1z, oz3 2 d03 i/o i1z, oz3 2 d03 i/o i1z, oz3 3 d04 i/o i1z, oz3 3 d04 i/o i1z, oz3 3 d04 i/o i1z, oz3 4 d05 i/o i1z, oz3 4 d05 i/o i1z, oz3 4 d05 i/o i1z, oz3 5 d06 i/o i1z, oz3 5 d06 i/o i1z, oz3 5 d06 i/o i1z, oz3 6 d07 i/o i1z, oz3 6 d07 i/o i1z, oz3 6 d07 i/o i1z, oz3 7 -ce1 i i3u 7 -ce1 i i3u 7 -cs0 i i3z 8 a10 i i1z 8 a10 i i1z 8 a10 2 i i1z 9 -oe i i3u 9 -oe i i3u 9 -ata sel i i3u 10 a09 i i1z 10 a09 i i1z 10 a09 2 i i1z 11 a08 i i1z 11 a08 i i1z 11 a08 2 i i1z 12 a07 i i1z 12 a07 i i1z 12 a07 2 i i1z 13 vcc power 13 vcc power 13 vcc i power 14 a06 i i1z 14 a06 i i1z 14 a06 2 i i1z 15 a05 i i1z 15 a05 i i1z 15 a05 2 i i1z 16 a04 i i1z 16 a04 i i1z 16 a04 2 i i1z 17 a03 i i1z 17 a03 i i1z 17 a03 2 i i1z 18 a02 i i1z 18 a02 i i1z 18 a02 i i1z 19 a01 i i1z 19 a01 i i1z 19 a01 i i1z 20 a00 i i1z 20 a00 i i1z 20 a00 i i1z 21 d00 i/o i1z,oz3 21 d00 i/o i1z,oz3 21 d00 i/o i1z,oz3 22 d01 i/o i1z,oz3 22 d01 i/o i1z,oz3 22 d01 i/o i1z,oz3 23 d02 i/o i1z,oz3 23 d02 i/o i1z,oz3 23 d02 i/o i1z,oz3 24 wp o ot3 24 -iois16 o ot3 24 -iocs16 o on3 25 -cd2 o ground 25 -cd2 o ground 25 -cd2 o ground 26 -cd1 o ground 26 -cd1 o ground 26 -cd1 o ground 27 d11 1 i/o i1z,oz3 27 d11 1 i/o i1z,oz3 27 d11 1 i/o i1z,oz3 28 d12 1 i/o i1z,oz3 28 d12 1 i/o i1z,oz3 28 d12 1 i/o i1z,oz3 29 d13 1 i/o i1z,oz3 29 d13 1 i/o i1z,oz3 29 d13 1 i/o i1z,oz3 30 d14 1 i/o i1z,oz3 30 d14 1 i/o i1z,oz3 30 d14 1 i/o i1z,oz3 31 d15 1 i/o i1z,oz3 31 d15 1 i/o i1z,oz3 31 d15 1 i/o i1z,oz3 32 -ce2 1 i i3u 32 -ce2 1 i i3u 32 -cs 1 i i1z 33 -vs1 o ground 33 -vs1 o ground 33 -vs1 o ground 34 -iord i i3u 34 -iord i i3u 34 -iord i i3z 35 -iowr i i3u 35 -iowr i i3u 35 -iowr i i3z 36 -we i i3u 36 -we i i3u 36 -we 3 i i3u
2001-09-05 8/52 thncfxxxmaa series preliminar y version pc card memory mode pc card i/o mode true ide mode pin num. signal name pin type in,out type pin num. signal name pin type in,out type pin num. signal name pin type in,out type 37 rdy/bsy o ot1 37 ireq o ot1 37 intrq o oz1 38 vcc power 38 vcc power 38 vcc power 39 -csel i i2z 39 -csel i i2z 39 -csel i i2u 40 -vs2 o open 40 -vs2 o open 40 -vs2 o open 41 reset i i2z 41 reset i i2z 41 -reset i i2z 42 -wait o ot1 42 -wait o ot1 42 iordy o on1 43 -inpack o ot1 43 -inpack o ot1 43 -inpack o oz1 44 -reg i i3u 44 -reg i i3u 44 -reg 3 i i3u 45 bvd2 i/o i1u, ot1 45 -spkr i/o i1u,ot1 45 -dasp i/o i1u,on1 46 bvd1 i/o i1u, ot1 46 -stschg i/o i1u,ot1 46 -pdiag i/o i1u,on1 47 d08 1 i/o i1z, oz3 47 d08 1 i/o i1z,oz3 47 d08 1 i/o i1z,oz3 48 d09 1 i/o i1z, oz3 48 d09 1 i/o i1z,oz3 48 d09 1 i/o i1z,oz3 49 d10 1 i/o i1z, oz3 49 d10 1 i/o i1z,oz3 49 d10 1 i/o i1z,oz3 50 gnd ground 50 gnd ground 50 gnd ground note: 1. these signals are required only for 16bit access and not required when installed in 8-bit systems. devices should allow for 3-state signals not to consume current. 2. should be grounded by the host. 3. should be tied to vcc by the host. 4. optional for cf+cards, required for compactflash stora g e cards.
2001-09-05 9/52 thncfxxxmaa series preliminar y version si si si signal description gnal description gnal description gnal description signal name dir. pin description a10 - a0 (pc card memory mode) a10 ? a0 (pc card i/o mode) a2 ? a0 (true ide mode) i i 8,10,11,12 14,15,16,17, 18,19,20 18,19,20 these address lines along with the ?reg signal are used to select the following: the i/o port address registers within the compactflash storage card or cf+card, the memory mapped port address registers within the compactflash storage card or cf+card, a byte in the card?s information structure and its configuration control and status registers. this signal is the same as the pc card memory mode signal. in true ide mode only a[2:0] are used to select the one of eight registers in the task file, the remaining address lines should be grounded by the host. bvd1 (pc card memory mode) -stschg (pc card i/o mode) status changed -pdiag (true ide mode) i/o 46 this signal is asserted high as bvd1 is not supported. this signal is asserted low to alert the host to changes in the rdy/-bsy and write protect states, while the i/o interface is configured. its use is controlled by the card config and status register. in the true ide mode, this input/output is the pass diagnostic signal in the master/slave handshake protocol. bvd2 (pc card memory mode) -spkr (pc card i/o mode) -dasp (true ide mode) i/o 45 this signal is asserted high as bvd2 is not supported. this line is the binary audio output from the card. if the card does not support the binary audio function, this line should be held negated. in the true ide mode, this input/output is the disk active/slave present signal in the master/slave handshake protocol. -cd1, -cd2 (pc card memory mode) -cd1, -cd2 (pc card i/o mode) -cd1, -cd2 (true ide mode) o 26,25 these card detect pins are connected to ground on the compactflash storage card or cf+card. they are used by the host to determine that the compactflash storage card or cf+card is fully inserted into its socket. this signal is the same for all modes. this signal is the same for all modes. -ce1, -ce2 (pc card memory mode) card enable -ce1, -ce2 (pc card i/o mode) card enable -cs0, -cs1 (true ide mode) i 7,32 these input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. ?ce2 always accesses the odd byte of the word, -ce1accesses the even byte or the odd byte of the word depending on a0 and ?ce2. a multiplexing scheme based on a0, -ce1, -ce2 allows 8 bit hosts to access all data on d0-d7. see tables 4-11, 4-12, 4-15, 4-16 and 4-17. this signal is the same as the pc card memory mode signal. in the true ide mode cs0 is the chip select for the task file registers while cs2 is used to select the alternate status register and the device control register.
2001-09-05 10/52 thncfxxxmaa series preliminar y version signal name dir. pin description -csel (pc card memory mode) -csel (pc card i/o mode) -csel (true ide mode) i 39 this signal is not used for this mode. this signal is not used for this mode. this internally pulled up signal is used to configure this device as a master or a slave when configured in the true ide mode. when this pin is grounded, this device is configured as a master. when the pin is open, this device is configured as a slave. d15 ? d00 (pc card memory mode) d15 ? d00 (pc card i/o mode) d15 ? d00 (true ide mode) i/o 31,30,29,28, 27,49,48,47, 6,5,4,3,2,23, 22,21 these lines carry the data, commands and status information between the host and the controller. d00 is the lsb of the even byte of the word. d08 is the lsb of the odd byte of the word. this signal is the same as the pc card memory mode signal. in true ide mode, all task file operations occur in byte mode on the low order bus d00?d07 while all data transfers are 16bit using d00?d15. gnd (pc card memory mode) gnd (pc card i/o mode) gnd (true ide mode) - 1, 50 ground this signal is the same for all modes. this signal is the same for all modes. -inpack (pc card memory mode) -inpack (pc card i/o mode) input acknowledge -inpack (true ide mode) o 43 this signal is not used in this mode. the input acknowledge signal is asserted by the compactflash storage card or cf+ card when the card is selected and responding to an i/o read cycle at the address that is on the address bus. this signal is used by the host to control the enable of any input data buffers between the compactflash storage card or cf+card and the cpu. in true ide mode this output signal is not used and should not be connected at the host. -iord (pc card memory mode) -iord (pc card i/o mode) -iord (true ide mode) i 34 this signal is not used in this mode. this is an i/o read strobe generated by the host. this signal gates i/o data onto the bus from the compactflash storage card or cf+card when the card is configured to use the i/o interface. in true ide mode, this signal has the same function as in pc card i/o mode. -iowr (pc card memory mode) -iowr (pc card i/o mode) -iowr (true ide mode) i 35 this signal is not used in this mode. the i/o write strobe pulse is used to clock i/o data on the card data bus into the compactflash strage card or cf+card controller registers when the compactflash storage card or cf+card is configured to use the i/o interface. the clocking will occur on the negative to positive edge of the signal(trailing edge). in true ide mode, this signal has the same function as in pc card i/o mode.
2001-09-05 11/52 thncfxxxmaa series preliminar y version signal name dir. pin description -oe (pc card memory mode) -oe (pc card i/o mode) -ata sel (true ide mode) i 9 this is an output enable strobe generated by the host interface. it is used to read data from the compactflash strage card or cf+card in memory mode and to read the cis and configuration registers. in pc card i/o mode, this signal is used to read the cis and configuration registers. to enable true ide mode this input should be grounded by the host. rdy/-bsy (pc card memory mode) -ireq (pc card i/o mode) intrq (true ide mode) o 37 in memory mode this signal is set high when the compactflash storage card or cf+card is ready to accept a new data transfer operation and held low when the card is busy. the host memory card socket must provide a pull-up resistor. at power up and at reset, the rdy/-bsy signal is held low(busy) until the compactflash storage card or cf+card has completed its power up or reset function. no access of any type should be made to the compactflash storage card or cf+card during this time. the rdy/-bsy signal is held high(disabled from being busy) whenever the following condition is true: the compactflash storage card or cf+card has been powered up with +reset continuously disconnected or asserted. i/o operation ?after the compactflash storage card or cf+card has been configured for i/o operation, this signal is used as ?interrupt request. this line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. in true ide mode signal is the active high interrupt request to the host. -reg (pc card memory mode) attribute memory select -reg (pc card i/o mode) -reg (true ide mode) i 44 this signal is used during memory cycles to distinguish between common memory and register (attribute) memory accesses. high for common memory, low for attribute memory. the signal must also be active (low) during i/o cycles when the i/o address is on the bus. in true ide mode this input signal is not used and should be connected to vcc by the host. reset (pc card memory mode) reset (pc card i/o mode) -reset (true ide mode) i 41 when the pin is high, this signal resets the compactflash storage card or cf+card. the compactflash storage card or cf+card is reset only at power up if this pin is left high or open from power-up. the compactflash storage card or cf+card is also reset when the soft reset bit in the card configuration option register is set. this signal is the same as the pc card memory mode signal. in the true ide mode this input pin is the active low hardware reset from the host. vcc (pc card memory mode) vcc (pc card i/o mode) vcc (true ide mode) - 13,38 +5v, +3.3v power this signal is the same for all modes. this signal is the same for all modes.
2001-09-05 12/52 thncfxxxmaa series preliminar y version signal name signal name signal name signal name dir. dir. dir. dir. pin pin pin pin description description description description -vs1 -vs2 (pc card memory mode) -vs1 -vs2 (pc card i/o mode) -vs1 -vs2 (true ide mode) o 33 40 voltage sense signals. ?vs1 is grounded so that the compactflash storage card or cf+card cis can be read at 3.3 volts and ?vs2 is reserved by pcmcia for a secondary voltage. this signal is the same for all modes. this signal is the same for all modes. -wait (pc card memory mode) -wait (pc card i/o mode) iordy (true ide mode) o 42 the ?wait signal is driven low by the compactflash storage card or cf+card to signal the host to delay completion of a memory or i/o cycle that is in progress. this signal is the same as the pc card memory mode signal. in true ide mode this output signal may be used as iordy. -we (pc card memory mode) -we (pc card i/o mode) -we (true ide mode) i 36 this is a signal driven by the host and used for strobing memory write data to the registers of the compactflash storage card storage card or cf+card when the card is configured in the memory interfacce mode. it is also used for writing the configuration registers. in pc card i/o mode, this signal is used for writing the configuration registers. in true ide mode this input signal is not used and should be connected to vcc by the host. wp (pc card memory mode) write protect -iois16 (pc card i/o mode) -iois 16 (true ide mode) o 24 memory mode ? the compactflash storage card or cf+card does not have a write protect switch. this signal is held low after the completion of the reset initialization sequence. i/o operation ? when the compactflash storage card or cf+card is configured for i/o operation pin 24 is used for the ?i/o selected is 16bit port (-iois16) function. a low signal indicates that a 16bit or odd byte only operation can be performed at the addressed port. in true ide mode this output signal is asserted low when this device is expecting a word data transfer cycle.
2001-09-05 13/52 thncfxxxmaa series preliminar y version access specifications 1 . 1 . 1 . 1 . attribute access specifications attribute access specifications attribute access specifications attribute access specifications when cis-rom region or configuration register region is accessed, read and write operations are executed under the condition of ? reg= ? l ? as follows. that region can be accessed by byte/world/old-byte modes, which are defined by pc card standard specifications. attribute read access mode attribute read access mode attribute read access mode attribute read access mode mode mode mode mode - - - -reg reg reg reg - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 a0 a0 a0 - - - -oe oe oe oe - - - -we we we we d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 standby mode x h h x x x high-z high-z byte access(8-bit) l h l l l h high-z even byte l h l h l h high-z invalid word access( 1 6-bit) l l l x l h invalid even byte odd byte access(8-bit) l l h x l h invalid high-z note: x: l or h attribute write access mode attribute write access mode attribute write access mode attribute write access mode mode mode mode mode - - - -reg reg reg reg - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 a0 a0 a0 - - - -oe oe oe oe - - - -we we we we d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 standby mode x h h x x x don ? t care don ? t care byte access(8-bit) l h l l h l don ? t care even byte l h l h h l don ? t care don ? t care word access( 1 6-bit) l l l x h l don ? t care even byte odd byte access(8-bit) l l h x h l don ? t care don ? t care note: x: l or h note: write cis-rom region is invalid. attribute access timing example attribute access timing example attribute access timing example attribute access timing example a0 to a10 -reg -ce2/-ce1 -oe -we dout din read cycle write cycle d0 to d15
2001-09-05 14/52 thncfxxxmaa series preliminar y version task file register access specifications task file register access specifications task file register access specifications task file register access specifications there are two cases of task file register mapping, one is mapped i/o address area, the other is mapped memory address area. each case of task file registers read and write operations is executed under the condition as follows. that area can be accessed by byte/world/odd byte modes, which are defined by pc card standard specifications. ( 1 ) ( 1 ) ( 1 ) ( 1 ) i/o address map i/o address map i/o address map i/o address map task file register read access mode ( 1 ) task file register read access mode ( 1 ) task file register read access mode ( 1 ) task file register read access mode ( 1 ) mode mode mode mode - - - -reg reg reg reg - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 a0 a0 a0 - - - -iord iord iord iord - - - -iowr iowr iowr iowr - - - -oe oe oe oe - - - -we we we we d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 standby mode x h h x x x x x high-z high-z byte access(8-bit) l h l l l h h h high-z even byte l h l h l h h h high-z odd byte word access( 1 6-bit) l l l x l h h h odd byte even byte odd byte access(8-bit) l l h x l h h h odd byte high-z note: x: l or h task file register write access mode ( 1 ) task file register write access mode ( 1 ) task file register write access mode ( 1 ) task file register write access mode ( 1 ) mode mode mode mode - - - -reg reg reg reg - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 a0 a0 a0 - - - -iord iord iord iord - - - -iowr iowr iowr iowr - - - -oe oe oe oe - - - -we we we we d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 standby mode x h h x x x x x don ? t care don ? t care byte access(8-bit) l h l l h l h h don ? t care even byte l h l h h l h h don ? t care odd byte word access( 1 6-bit) l l l x h l h h odd byte even byte odd byte access(8-bit) l l h x h l h h odd byte don ? t care note: x: l or h task file register access timing example ( task file register access timing example ( task file register access timing example ( task file register access timing example ( 1 1 1 1 ) ) ) ) a0 to a10 -reg -ce2/-ce1 -iord -iowr dout din read cycle write cycle d0 to d15
2001-09-05 15/52 thncfxxxmaa series preliminar y version memory address map memory address map memory address map memory address map task file register read access mode (2) task file register read access mode (2) task file register read access mode (2) task file register read access mode (2) mode mode mode mode - - - -reg reg reg reg - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 a0 a0 a0 - - - -oe oe oe oe - - - -we we we we - - - -iord iord iord iord - - - -iowr iowr iowr iowr d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 standby mode x h h x x x x x high-z high-z byte access(8-bit) h h l l l h h h high-z even byte h h l h l h h h high-z odd byte word access( 1 6-bit) h l l x l h h h odd byte even byte odd byte access(8-bit) h l h x l h h h odd byte high-z note: x: l or h task file register write access mode (2) task file register write access mode (2) task file register write access mode (2) task file register write access mode (2) mode mode mode mode - - - -reg reg reg reg - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 a0 a0 a0 - - - -oe oe oe oe - - - -we we we we - - - -iord iord iord iord - - - -iowr iowr iowr iowr d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 standby mode x h h x x x x x don ? t care don ? t care byte access(8-bit) h h l l h l h h don ? t care even byte h h l h h l h h don ? t care odd byte word access( 1 6-bit) h l l x h l h h odd byte even byte odd byte access(8-bit) h l h x h l h h odd byte don ? t care note: x: l or h task file register access timing example (2) task file register access timing example (2) task file register access timing example (2) task file register access timing example (2) a0 to a10 -reg -ce2/-ce1 -oe -we dout din read cycle write cycle d0 to d15
2001-09-05 16/52 thncfxxxmaa series preliminar y version true ide mode true ide mode true ide mode true ide mode the card can be configured in a true ide this card is configured in this mode only when the-oe input signal is asserted gnd by the host. in this true ide mode attribute registers are not accessible from the host. only i/o operation to the task file and data register is allowed. if this card is configured during power on sequence, data register is accessed in word ( 1 6-bit). the card permits 8-bit accessed if the user issues a set feature command to put the device in 8-bit mode. true i true i true i true ide mode read i/o function de mode read i/o function de mode read i/o function de mode read i/o function mode mode mode mode - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 to a2 a0 to a2 a0 to a2 a0 to a2 - - - -iord iord iord iord - - - -owr owr owr owr d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 invalid mode l l x x x high-z high-z standby mode h h x x x high-z high-z data register access h l 0 l h odd byte even byte alternate status access l h 6h l h high-z status out other task file access h l 1 -7h l h high-z data note: x: l or h true ide mode write i/o function true ide mode write i/o function true ide mode write i/o function true ide mode write i/o function mode mode mode mode - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a0 to a2 a0 to a2 a0 to a2 a0 to a2 - - - -iord iord iord iord - - - -owr owr owr owr d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d8 to d 1 5 d0 to d7 d0 to d7 d0 to d7 d0 to d7 invalid mode l l x x x don ? t care don ? t care standby mode h h x x x don ? t care don ? t care data register access h l 0 h l odd byte even byte control register access l h 6h h l don ? t care control in other task file access h l 1 -7h h l don ? t care data note: x: l or h true ide mode i/o access timing example true ide mode i/o access timing example true ide mode i/o access timing example true ide mode i/o access timing example a0 to a2 -ce -iord -iowr -iois16 dout read cycle write cycle write cycle write cycle write cycle d0 to d15 din
2001-09-05 17/52 thncfxxxmaa series preliminar y version configuration register specifications configuration register specifications configuration register specifications configuration register specifications this card supports four configuration registers for the purpose of the configuration and observation of this card. these registers can be used in memory card mode and i/o card mode. in true ide mode, these registers can not be used. 1 . 1 . 1 . 1 . configuration option register(address 200h) configuration option register(address 200h) configuration option register(address 200h) configuration option register(address 200h) this register is used for the configuration of the card configuration status and for the issuing soft reset to the card. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit bit bit bit0 0 0 0 sreset levlreq index note: initial value: 00h name name name name r/w r/w r/w r/w function function function function sreset r/w setting this bit to ? 1 ? , places the card in the reset state (card hard reset). this operation is equal to hard reset, except this bit is not cleared. then this bit set to ? 0 ? , places the card in the reset state of hard reset (this bit is set to ? 0 ? by hard reset). card configuration status is reset and the card internal initialized operation starts when card hard reset is executed, so next access to the card should be the same sequence as the power on sequence. levlreq (host->) r/w this bit sets to ? 0 ? when pulse mode interrupt is selected, and ? 1 ? when level mode interrupt is selected. index (host->) r/w this bits is used for select operation mode of the card as follows. when power on, card hard reset and soft reset, this data is ? 000000 ? for the purpose of memory card interface recognition. index bit assignment index bit assignment index bit assignment index bit assignment index bit index bit index bit index bit 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 card mode card mode card mode card mode task file register address task file register address task file register address task file register address mapping mode mapping mode mapping mode mapping mode 0 0 0 0 0 0 memory card 0h to fh, 400h to 7ffh memory mapped 0 0 0 0 0 1 i/o card xx0h to xxfh contiguous i/o mapped 0 0 0 0 1 0 i/o card 1 f0h to 1 f7h,3f6h to 3f7h primary i/o mapped 0 0 0 0 1 1 i/o card 1 f0h to 1 77h,376h to 3f7h secondary i/o mapped
2001-09-05 18/52 thncfxxxmaa series preliminar y version 2. 2. 2. 2. configuration and status register ( configuration and status register ( configuration and status register ( configuration and status register (address 202h) address 202h) address 202h) address 202h) this register is used for observing the state of the card. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 chged sigchg iois8 0 0 pwd intr 0 note: initial value: 00h name name name name r/w r/w r/w r/w function function function function chged (card->) r this bit indicates that crdy/-bsy bit on pin replacement register is set to ? 1 ? . when chged bit is set to ? 1 ? , -stschg pin is held ? l ? at the condition of sigchg bit set to ? 1 ? and the card configured for the i/o interface. sigchg (host->) r/w this bit is set or reset by the host for enabling and disabling the status-change signal (-stschg pin). when the card is configured i/o card interface and this bit is set ? 1 ? , -stschg pin is controlled by chged bit. if this bit is set to ? 0 ? , -stschg pin is kept ? h ? . iois8 (host->) r/w the host sets this field to ? 1 ? when it can provide i/o cycles only with on 8 bit data bus (d7 to d0). pwd (host->) r/w when this bit is set to ? 1 ? , the card enters sleep state (power down mode). when this bit is reset to ? 0 ? , the card transfers to idle state (active mode). rrdy/bsy bit on pin replacement register becomes busy when this bit is changed. rrdy/bsy will not become ready until the power state requested has been entered. this card automatically powers down when it is idle and powers back up when it receives a command. intr (card->) r this bit indicates the internal state of the interrupt request. this bit state is available whether i/o card interface has been configured or not. this signal remains true until the condition, which caused the interrupt request, has been serviced. if the ? ien bit in the device control register disables interrupts, this bit is a zero.
2001-09-05 19/52 thncfxxxmaa series preliminar y version 3. 3. 3. 3. pin replacement register (address 204h) pin replacement register (address 204h) pin replacement register (address 204h) pin replacement register (address 204h) this register is used for providing the state of ? ireq signal when the card configured i/o card interface. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 0 0 crdy/-bsy 0 1 1 rrdy/-bsy 0 note: initial value: 0ch name name name name r/w r/w r/w r/w function function function function crdy/-bsy (host->) r/w this bit is set to ? 1 ? when the rrdy/-bsy bit changes state. the host may also write this bit. rrdy/-bsy (host->) r when read, this bit indicates +ready pin states. when written, this bit is used for crdy/-bsy bit masking. 4. 4. 4. 4. socket and copy register (address 206h) socket and copy register (address 206h) socket and copy register (address 206h) socket and copy register (address 206h) this register is used for identification of the card from the other cards. host can read and write this register. host should set this register before this card ? s configuration option register set. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 0 0 0 drv# 0 0 0 0 note: initial value: 00h name name name name r/w r/w r/w r/w function function function function drv# (host->) r these fields are used for the configuration of the plural cards. when host configures the plural cards, written the card ? s copy number in this field. in this way, host can perform the card ? s master/slave organization.
2001-09-05 20/52 thncfxxxmaa series preliminar y version cis cis cis cis information information information information cis information of compactflash card is defined as follows. address address address address data data data data description of contents description of contents description of contents description of contents cis function cis function cis function cis function 000h 0 1 h cistpl_device tuple code 002h 03h tpl_link tuple link 004h d9h device information tuple data 006h 0 1 h device information tuple data 008h ffh end marker end of tuple 00ah 1 ch cistpl_device_oc tuple code 00ch 04h tpl_link tuple link 00eh 03h conditions information tuple data 0 1 0h d9h device information tuple data 0 1 2h 0 1 h device information tuple data 0 1 4h ffh end marker end of tuple 0 1 6h 1 8h cistpl_jedec_c tuple code 0 1 8h 02h tpl_link tuple link 0 1 ah dfh pcmcia s manufacture s jedec id code tuple data 0 1 ch 0 1 h pcmcia s jedec device code tuple data 0 1 eh 20h cistpl_manfid tuple code 020h 04h tpl_link tuple link 022h 00h low byte of manufacturer's id code tuple data 024h 00h high byte of manufacturer's id code tuple data 026h 00h low byte of product code tuple data 028h 00h high byte of product code tuple data 02ah 1 5h cistpl_vers_ 1 tuple code 02ch 20h tpl_link tuple link 02eh 04h tpllv 1 _major tuple data 030h 0 1 h tpllv 1 _minor tuple data 032h xxh ' ' (vender specific strings) tuple data 034h xxh ' ' (vender specific strings) tuple data 036h xxh ' ' (vender specific strings) tuple data 038h xxh ' ' (vender specific strings) tuple data 03ah xxh ' ' (vender specific strings) tuple data 03ch xxh ' ' (vender specific strings) tuple data 03eh xxh ' ' (vender specific strings) tuple data 040h xxh ' ' (vender specific strings) tuple data 042h xxh ' ' (vender specific strings) tuple data 044h xxh ' ' (vender specific strings) tuple data 046h xxh ' ' (vender specific strings) tuple data 048h xxh ' ' (vender specific strings) tuple data 04ah xxh ' ' (vender specific strings) tuple data 04ch xxh ' ' (vender specific strings) tuple data
2001-09-05 21/52 thncfxxxmaa series preliminar y version 04eh xxh ' ' (vender specific strings) tuple data 050h xxh ' ' (vender specific strings) tuple data 052h xxh ' ' (vender specific strings) tuple data 054h xxh ' ' (vender specific strings) tuple data 056h xxh ' ' (vender specific strings) tuple data 058h 00h null terminator tuple data 05ah xxh ' ' (vender specific strings) tuple data 05ch xxh ' ' (vender specific strings) tuple data 05eh xxh ' ' (vender specific strings) tuple data 060h xxh ' ' (vender specific strings) tuple data 062h xxh ' ' (vender specific strings) tuple data 064h xxh ' ' (vender specific strings) tuple data 066h xxh ' ' (vender specific strings) tuple data 068h xxh ' ' (vender specific strings) tuple data 06ah 00h null terminator tuple data 06ch ffh end marker end of tuple 06eh 2 1 h cistpl_funcid tuple code 070h 02h tpl_link tuple link 072h 04h ic card function code tuple data 074h 0 1 h system initialization bit mask tuple data 076h 22h cistpl_funce tuple code 078h 02h tpl_link tuple link 07ah 0 1 h type of extended data tuple data 07ch 0 1 h function information tuple data 07eh 22h cistpl_funce tuple code 080h 03h tpl_link tuple link 082h 02h type of extended data tuple data 084h 0ch function information tuple data 086h 0fh function information tuple data 088h 1 ah cistpl_config tuple code 08ah 05h tpl_link tuple link 08ch 0 1 h size field tuple data 08eh 03h index number of last entry tuple data 090h 00h configuration register base address (low) tuple data 092h 02h configuration register base address (high) tuple data 094h 0fh configuration register present mask tuple data 096h 1 bh cistpl_cftable_entry tuple code 098h 08h tpl_link tuple link 09ah c0h configuration index byte tuple data 09ch c0h interface descriptor tuple data 09eh a 1 h feature select tuple data 0a0h 0 1 h vcc selection byte tuple data 0a2h 55h nom v paramete tuple data 0a4h 08h memory length (256 byte pages) tuple data
2001-09-05 22/52 thncfxxxmaa series preliminar y version 0a6h 00h memory length (256 byte pages) tuple data 0a8h 20h misc features tuple data 0aah 1 bh cistpl_cftable_entry tuple code 0ach 06h tpl_link tuple link 0aeh 00h configuration index byte tuple data 0b0h 0 1 h feature select tuple data 0b2h 2 1 h vcc selection byte tuple data 0b4h b5h nom v parameter tuple data 0b6h 1 eh nom v parameter tuple data 0b8h 4dh peak i parameter tuple data 0bah 1 bh cistpl_cftable_entry tuple code 0bch 0ah tpl_link tuple link 0beh c 1 h configuration index byte tuple data 0c0h 4 1 h interface descriptor tuple data 0c2h 99h feature select tuple data 0c4h 0 1 h vcc selection byte tuple data 0c6h 55h nom v parameter tuple data 0c8h 64h i/o param tuple data 0cah f0h irq parameter tuple data 0cch ffh irq request mask tuple date 0ceh ffh irq request mask tuple data 0d0h 20h misc features tuple data 0d2h 1 bh cistpl_cftable_entry tuple code 0d4h 06h tpl_link tuple link 0d6h 0 1 h configuration index byte tuple data 0d8h 0 1 h feature select tuple data 0dah 2 1 h vcc selection byte tuple data 0dch b5h nom v parameter tuple data 0deh 1 eh nom v parameter tuple data 0e0h 4dh peak i parameter tuple data 0e2h 1 bh cistpl_cftable_entry tuple code 0e4h 0fh tpl_link tuple link 0e6h c2h configuration index byte tuple data 0e8h 4 1 h interface descriptor tuple data 0eah 99h feature select tuple data 0ech 0 1 h vcc selection byte tuple data 0eeh 55h nom v parameter tuple data 0f0h eah i/o param tuple data 0f2h 6 1 h i/o range length and size tuple data 0f4h f0h base address tuple data 0f6h 0 1 h base address tuple data 0f8h 07h address length tuple data 0fah f6h base address tuple data 0fch 03h base address tuple data
2001-09-05 23/52 thncfxxxmaa series preliminar y version 0feh 0 1 h address length tuple data 1 00h eeh irq parameter tuple data 1 02h 20h misc features tuple data 1 04h 1 bh cistpl_cftable_entry tuple code 1 06h 06h tpl_link tuple link 1 08h 02h configuration index byte tuple data 1 0ah 0 1 h feature select tuple data 1 0ch 2 1 h vcc selection byte tuple data 1 0eh b5h nom v parameter tuple data 11 0h 1 eh nom v parameter tuple data 11 2h 4dh peak i parameter tuple data 11 4h 1 bh cistpl_cftable_entry tuple code 11 6h 0fh tpl_link tuple link 11 8h c3h configuration index byte tuple data 11 ah 4 1 h interface descriptor tuple data 11 ch 99h feature select tuple data 11 eh 0 1 h vcc selection byte tuple data 1 20h 55h nom v parameter tuple data 1 22h eah i/o param tuple data 1 24h 6 1 h i/o range length and size tuple data 1 26h 70h base address tuple data 1 28h 0 1 h base address tuple data 1 2ah 07h address length tuple data 1 2ch 76h base address tuple data 1 2eh 03h base address tuple data 1 30h 0 1 h address length tuple data 1 32h eeh irq parameter tuple data 1 34h 20h misc features tuple data 1 36h 1 bh cistpl_cftable_entry tuple code 1 38h 06h tpl_link tuple link 1 3ah 03h configuration index byte tuple data 1 3ch 0 1 h feature select tuple data 1 3eh 2 1 h vcc selection byte tuple data 1 40h b5h nom v parameter tuple data 1 42h 1 eh nom v parameter tuple data 1 44h 4dh peak i parameter tuple data 1 46h 1 4h cistpl_no_link tuple code 1 48h 00h tpl_link tuple link 1 4ah ffh cistpl_end end of tuple
2001-09-05 24/52 thncfxxxmaa series preliminar y version task file register specification task file register specification task file register specification task file register specification these registers are used for reading and writing the storage data in this card. these registers are mapped five types by the configuration of index in configuration option register. the decoded addresses are shown as follows. memory map (index=0) memory map (index=0) memory map (index=0) memory map (index=0) - - - -reg reg reg reg a 1 0 a 1 0 a 1 0 a 1 0 a9 to a4 a9 to a4 a9 to a4 a9 to a4 a3 a3 a3 a3 a2 a2 a2 a2 a 1 a 1 a 1 a 1 a0 a0 a0 a0 offset offset offset offset - - - -oe=l oe=l oe=l oe=l - - - -we=l we=l we=l we=l 1 0 x 0 0 0 0 0h data register data register 1 0 x 0 0 0 1 1 h error register feature register 1 0 x 0 0 1 0 2h sector count register sector count register 1 0 x 0 0 1 1 3h sector number register sector number register 1 0 x 0 1 0 0 4h cylinder low register cylinder low register 1 0 x 0 1 0 1 5h cylinder high register cylinder high register 1 0 x 0 1 1 0 6h drive head register drive head register 1 0 x 0 1 1 1 7h status register command register 1 0 x 1 0 0 0 8h dup. even data register dup. even data register 1 0 x 1 0 0 1 9h dup. odd data register dup. odd data register 1 0 x 1 1 0 1 dh dup. error register dup. feature register 1 0 x 1 1 1 0 eh alt. status register device control register 1 0 x 1 1 1 1 fh drive address register reserved 1 1 x x x x 0 8h even data register even data register 1 1 x x x x 1 9h odd data register odd data register
2001-09-05 25/52 thncfxxxmaa series preliminar y version contiguous i/o map (index= 1 ) contiguous i/o map (index= 1 ) contiguous i/o map (index= 1 ) contiguous i/o map (index= 1 ) - - - -reg reg reg reg a 1 0 to a4 a 1 0 to a4 a 1 0 to a4 a 1 0 to a4 a3 a3 a3 a3 a2 a2 a2 a2 a 1 a 1 a 1 a 1 a0 a0 a0 a0 offset offset offset offset - - - -iord=l iord=l iord=l iord=l - - - -iowr=l iowr=l iowr=l iowr=l 0 x 0 0 0 0 0h data register data register 0 x 0 0 0 1 1 h error register feature register 0 x 0 0 1 0 2h sector count register sector count register 0 x 0 0 1 1 3h sector number register sector number register 0 x 0 1 0 0 4h cylinder low register cylinder low register 0 x 0 1 0 1 5h cylinder high register cylinder high register 0 x 0 1 1 0 6h drive head register drive head register 0 x 0 1 1 1 7h status register command register 0 x 1 0 0 0 8h dup. even data register dup. even data register 0 x 1 0 0 1 9h dup. odd data register dup. odd data register 0 x 1 1 0 1 dh dup. error register dup. feature register 0 x 1 1 1 0 eh alt. status register device control register 0 x 1 1 1 1 fh drive address register reserved primary i/o map (index=2) primary i/o map (index=2) primary i/o map (index=2) primary i/o map (index=2) - - - -reg reg reg reg a 1 0 a 1 0 a 1 0 a 1 0 a9 to a4 a9 to a4 a9 to a4 a9 to a4 a3 a3 a3 a3 a2 a2 a2 a2 a 1 a 1 a 1 a 1 a0 a0 a0 a0 - - - -iord=l iord=l iord=l iord=l - - - -iowr=l iowr=l iowr=l iowr=l 0 x 1 fh 0 0 0 0 data register data register 0 x 1 fh 0 0 0 1 error register feature register 0 x 1 fh 0 0 1 0 sector count register sector count register 0 x 1 fh 0 0 1 1 sector number register sector number register 0 x 1 fh 0 1 0 0 cylinder low register cylinder low register 0 x 1 fh 0 1 0 1 cylinder high register cylinder high register 0 x 1 fh 0 1 1 0 drive head register drive head register 0 x 1 fh 0 1 1 1 status register command register 0 x 3fh 0 1 1 0 alt. status register device control register 0 x 3fh 0 1 1 1 drive address register reserved
2001-09-05 26/52 thncfxxxmaa series preliminar y version secondary i/o map (index=3) secondary i/o map (index=3) secondary i/o map (index=3) secondary i/o map (index=3) - - - -reg reg reg reg a 1 0 a 1 0 a 1 0 a 1 0 a9 to a4 a9 to a4 a9 to a4 a9 to a4 a3 a3 a3 a3 a2 a2 a2 a2 a 1 a 1 a 1 a 1 a0 a0 a0 a0 - - - -iord=l iord=l iord=l iord=l - - - -iowr=l iowr=l iowr=l iowr=l 0 x 1 7fh 0 0 0 0 data register data register 0 x 1 7fh 0 0 0 1 error register feature register 0 x 1 7fh 0 0 1 0 sector count register sector count register 0 x 1 7fh 0 0 1 1 sector number register sector number register 0 x 1 7fh 0 1 0 0 cylinder low register cylinder low register 0 x 1 7fh 0 1 0 1 cylinder high register cylinder high register 0 x 1 7fh 0 1 1 0 drive head register drive head register 0 x 1 7fh 0 1 1 1 status register command register 0 x 37fh 0 1 1 0 alt. status register device control register 0 x 37fh 0 1 1 1 drive address register reserved true ide mode i/o map true ide mode i/o map true ide mode i/o map true ide mode i/o map - - - -ce2 ce2 ce2 ce2 - - - -ce 1 ce 1 ce 1 ce 1 a2 a2 a2 a2 a 1 a 1 a 1 a 1 a0 a0 a0 a0 - - - -iord=l iord=l iord=l iord=l - - - -iowr=l iowr=l iowr=l iowr=l 1 0 0 0 0 data register data register 1 0 0 0 1 error register feature register 1 0 0 1 0 sector count register sector count register 1 0 0 1 1 sector number register sector number register 1 0 1 0 0 cylinder low register cylinder low register 1 0 1 0 1 cylinder high register cylinder high register 1 0 1 1 0 drive head register drive head register 1 0 1 1 1 status register command register 0 1 1 1 0 alt. status register device control register 0 1 1 1 1 drive address register reserved
2001-09-05 27/52 thncfxxxmaa series preliminar y version 1 .data register: 1 .data register: 1 .data register: 1 .data register: this register is a 1 6-bit register that has read/write ability, and it is used for transferring 1 sector data between the card and the host. this register can be accessed in word mode and byte mode. this register overlaps the error or feature register. bit 1 5 bit 1 5 bit 1 5 bit 1 5 bit 1 4 bit 1 4 bit 1 4 bit 1 4 bit 1 3 bit 1 3 bit 1 3 bit 1 3 bit 1 2 bit 1 2 bit 1 2 bit 1 2 bit 11 bit 11 bit 11 bit 11 bit 1 0 bit 1 0 bit 1 0 bit 1 0 bit9 bit9 bit9 bit9 bit8 bit8 bit8 bit8 bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 d0 to d 1 5 2.error register: 2.error register: 2.error register: 2.error register: this register is a read only register, and it is used for analyzing the error content at the card accessing. this register is valid when the bsy bit in status register and alternate status register are set to ? 0 ? (ready). bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 bbk unc ? 0 ? idnf ? 0 ? abrt ? 0 ? amnf bit bit bit bit name name name name function function function function 7 bbk(bad block detected) this bit is set when a bad block is detected in requester id field. 6 unc(data ecc error) this bit is set when uncorrectable error is occurred at reading the card. 4 idnf(id not found) the requested sector id is in error or cannot be found. 2 abrt(aborted command) this bit is set if the command has been abor t ed because of the card status condition.(not ready, write fault, invalid command, etc.) 0 amnf(address mark not found) this bit is set in case of a general error. 3.feature register: 3.feature register: 3.feature register: 3.feature register: this register is write-only register, and provides information regarding features of the drive that the host wishes to utilize. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 feature byte 5. sector count register: sector count register: sector count register: sector count register: this register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the card. if the value of this register is zero, a count of 256 sectors is specified. in plural sector transfer, if not successfully completed, the register contains the number of sectors, which need to be transferred in order to complete, the request. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 sector count byte
2001-09-05 28/52 thncfxxxmaa series preliminar y version 5.sector number register: 5.sector number register: 5.sector number register: 5.sector number register: this register contains the starting sector number, which is started by following sector transfer command. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 sector number byte 6.cylinder low register: 6.cylinder low register: 6.cylinder low register: 6.cylinder low register: this register contains the low 8-bit of the starting cylinder address, which is started by following sector transfer command. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 cylinder low byte 7.cylinder high register: 7.cylinder high register: 7.cylinder high register: 7.cylinder high register: this register contains the high 8-bit of the starting cylinder address, which is started by following sector transfer command. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 cylinder high byte 8.drive head register: 8.drive head register: 8.drive head register: 8.drive head register: this register is used for selecting the drive number and head number for the following command. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 1 lba 1 drv head number bit bit bit bit name name name name function function function function 7 1 this bit is set to ? 1 ? . 6 lba lba is a flag to select either cylinder/head/sector (chs) or logical block address (lba) mode. when lba =0, chs mode is selected. when lba= 1 , lba mode is selected. in lba mode, the logical block address is interrupted as follows: lba07-lba00 sector number register d7-d0. lba 1 5-lba08 cylinder low register d7-d0. lba23-lba 1 6 cylinder high register d7-d0. lba27-lba24 drive / head register bits hs3-hs0. 5 1 this bit is set to ? 1 ? . 4 drv(drive select) this bit is used for selecting the mas t er (card 0)and slave(card 1 ) in master/slave organization. the card is set to be card 0 or 1 by using drv# of the socket and copy register. 3 head number this bit is used for selecting the head number for the following command. bit 3 is msb.
2001-09-05 29/52 thncfxxxmaa series preliminar y version 9.status 9.status 9.status 9.status register: register: register: register: this register is read only register, and it indicates the card status of command execution. when this register is read in configured i/o card mode (index= 1 ,2,3) and level interrupt mode, -ireq is negated. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 bsy drdy dwf dsc drq corr idx err bit bit bit bit name name name name function function function function 7 bsy(busy) this bit is set when the card internal operation is executing. when this bit is set to ? 1 ? , other bits in this register are invalid. 6 drvy(drive ready) if this bit and dsc bit are set to ? 1 ? , the card is capable of receiving the read or write or seek requests. if this bit is set to ? 0 ? , the card prohibits these requests. 5 dwf(drive write fault) this bit is set if this card indicates the write fault status. 4 dsc(drive seek complete) this bit is set when the drive seeks complete. 3 drq(data request) this bit is set when the information can be transferred between the host and data register. this bit is cleared when the card receives the other command. 2 corr(corrected data) this bit is set when a correctable data error has been occurred and the data has been corrected. 1 idx(index) this bit is always set to ? 0 ? . 0 err(error) this bit is set when the previous command has ended in some type of error. the error information is set in this error register or other status registers. this bit is cleared by the next command. 1 0.alternate status register: 1 0.alternate status register: 1 0.alternate status register: 1 0.alternate status register: this register is the same as status register in physically, so the bit assignment refers to previous item of status register. but this register is different from status register that ? ireq is not negated when data read. 11 .command register: 11 .command register: 11 .command register: 11 .command register: this register is write only register, and it is used for writing the command to execute the requested operation. the command codes is written in the command register, after the parameter is written in the task file when the card is in ready state.
2001-09-05 30/52 thncfxxxmaa series preliminar y version used parameter used parameter used parameter used parameter command command command command command code command code command code command code fr fr fr fr sc sc sc sc sn sn sn sn cy cy cy cy dr dr dr dr hd hd hd hd lba lba lba lba check power mode e5h or 98h n n n n y n n execute drive diagnostic 90h n n n n y n n erase sector c0h n y y y y y y format track 50h n y n y y y y identify drive ech n n n n y n n idle e3h or 97h n y n n y n n idle immediate e 1 h or 95h n n n n y n n initialize drive parameters 9 1 h n y n n y y n read buffer e4h n n n n y n n read multiple c4h n y y y y y y read long sector 22h or 23h n n y y y y y read sector 20h or 2 1 h n y y y y y y read verify sector 40h or 4 1 h n y y y y y y recalibrate 1 xh n n n n y n n request sense 03h n n n n y n n seek 7xh n n y y y y y set features efh y n n n y n n set multiple mode c6h n y n n y n n set sleep mode e6h or 99h n n n n y n n stand by e2h or 96h n n n n y n n stand by immediate e0h or 94h n n n n y n n translate sector 87h n y y y y y y wear level f5h n n n n y y n write buffer e8h n n n n y n n write long sector 32h or 33h n n y y y y y write multiple c5h n y y y y y y write multiple w/o erase cdh n y y y y y y write sector 30h or 3 1 h n y y y y y y write sector w/o erase 38h n y y y y y y write verify 3ch n y y y y y y
2001-09-05 31/52 thncfxxxmaa series preliminar y version note: fr: feature register sc: sector count register sn: sector number register cy: cylinder register dr: drv bit of drive head register hd: head number of drive head register lba: logical block address mode supported y: the register contains a valid parameter for this command n: the register does not contain a valid parameter for this command 1 2. device control register: 1 2. device control register: 1 2. device control register: 1 2. device control register: this register is write only register, and it is used for controlling the card interrupt request and issuing an ata soft reset to the card. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 x x x x 1 srst nien 0 bit bit bit bit name name name name function function function function 7to 4 x don ? t care 3 1 this bit is set to ? 1 ? . 2 srst(software reset) this bit is set to ? 1 ? in order to force the card to perform task file reset operation. this does not change the card configuration registers as a hardware reset does. the card remains in reset until this bit is reset to ? 0 ? . 1 nien(interrupt enable) this bit is used for enabling ? ireq. when this bit is set to ? 0 ? , -ireq is enabled. when this bit is set to ? 1 ? , -ireq is disabled. 0 0 this bit is set to ? 0 ? . 1 3.drive address register: 1 3.drive address register: 1 3.drive address register: 1 3.drive address register: this register is read only register, and it is used for confirming the drive status. this register is provides for compatibility with the at disk drive interface. it is recommended that this register is not mapped into the host ? s i/o space because of potential conflicts on bit7. bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit5 bit5 bit5 bit5 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit 1 bit 1 bit 1 bit 1 bit0 bit0 bit0 bit0 x nwtg nhs3 nhs2 nhs 1 nhs0 nds 1 nds0 bit bit bit bit name name name name function function function function 7 x this bit is unknown. 6 nwtg(writing gate) this bit is unknown. 5 to 2 nhs3-0(head select3-0) these bits is the negative value of head select bits(bit 3 to 0)in drive/head register. 1 nds 1 (idrive select 1 ) this bit is unknown. 0 nds0(idrive select0) this bit is unknown.
2001-09-05 32/52 thncfxxxmaa series preliminar y version ata command specifications ata command specifications ata command specifications ata command specifications this table summarizes the ata command set with the paragraphs. following shows the supported commands and command codes, which are written in command registers. ata command set ata command set ata command set ata command set no. no. no. no. command set command set command set command set code code code code fr fr fr fr sc sc sc sc s s s sn n n n cy cy cy cy dr dr dr dr hd hd hd hd lsb lsb lsb lsb 1 check power mode e5h or 98h y 2 execute drive diagnostic 90h y 3 erase sector(s) c0h y y y y y y 4 format track 50h y y y y y 5 identify drive ech y 6 idle e3h or 97h y y 7 idle immediate e 1 h or 95h y 8 initialize drive parameters 9 1 h y y y 9 read buffer e4h y 1 0 read multiple c4h y y y y y y 11 read long sector 22h,23h y y y y y 1 2 read sector(s) 20h,2 1 h y y y y y y 1 3 read verify sector(s) 40h, 4 1 h y y y y y y 1 4 recalibrate 1 xh y 1 5 request sense 03h y 1 6 seek 7xh y y y y y 1 7 set features efh y y 1 8 set multiple mode c6h y y 1 9 set sleep mode e6h or 99h y 20 stand by e2h or 96h y 2 1 stand by immediate e0h or 94h y 22 translate sector 87h y y y y y y 23 wear level f5h y y 24 write buffer e8h y 25 write long sector 32h or 33h y y y y y 26 write multiple c5h y y y y y y 27 write multiple w/o erase cdh y y y y y y 28 write sector 30h or 3 1 h y y y y y y 29 write sector w/o erase 38h y y y y y y 30 write verify 3ch y y y y y y
2001-09-05 33/52 thncfxxxmaa series preliminar y version note fr feature register sc sector count register (00h to ffh) sn sector number register (0 1 h to 20h) cy cylinder low/high register dr drive bit of drive/head register hd head no.(0 to 3) of drive/head register y set up not set up 1 . check power mode (code: e5h or 98h): this command checks the power mode. 2. execute drive diagnostic (code: 90h): this command performs the internal diagnostic tests implemented by the card. 3. erase sector(s)(code: c0h): this command is used to erase data sectors. 4. format track (code: 50h): this command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically ffh or 00h). to remain host backward compatible, the card expects one sector (5 1 2bytes) of data from the host to follow the command with same protocol as the write sector command. 5. identify drive (code: ech): this command enables the host to receive parameter information from the card.
2001-09-05 34/52 thncfxxxmaa series preliminar y version identify drive information identify drive information identify drive information identify drive information word address word address word address word address default value default value default value default value total bytes total bytes total bytes total bytes data field type information data field type information data field type information data field type information 0 848ah 2 general configuration bit-significant information 1 xxxx 2 default number of cylinders 2 0000h 2 reserved 3 00xxh 2 default number of heads 4 0000h 2 number of unformatted bytes per track 5 xxxx 2 number of unformatted bytes per sector 6 xxxx 2 default number of sectors per track 7 to 8 xxxx 4 number of sectors per card(word7=msw,words=lsw) 9 0000h 2 reserved 1 0 to 1 9 xxxx 20 serial number in ascii 20 000 1 h 2 buffer type(single ported) 2 1 0004h 2 buffer size in 5 1 2 byte increments 22 0004h 2 # of ecc bytes passed on read/write long commands 23 to 46 xxxx 48 firmware revision in ascii etc. 47 000 1 h 2 maximum of 1 sector on read/write multiple command 48 0000h 2 double word not supported 49 0200h 2 capabilities: dma not supported(bit 8), lba supported (bi 9) 50 0000h 2 reserved 5 1 0200h 2 pio data transfer cycle timing mode 2 52 0000h 2 dma data transfer cycle timing mode not supported 53 to 58 xxxx 1 2 reserved 59 0 1 0 1 h 2 multiple sector setting is valid 60 to 6 1 xxxx 4 total number of sectors addressable in lba mode 62 to 255 0000h 388 reserved 6. idle (code: e3h or 97h): this command causes the card to set bsy, enter the idle mode, clear bsy and generate an interrupt. if sector count is non-zero, the automatic power down mode is enabled. if the sector count is zero, the automatic power mode is disabled. 7. idle immediate (code: e 1 h or 95h): this command causes the card to set bsy, enter the idle(read) mode, clear bsy and generate an interrupt. 8. initialize drive parameters (code: 9 1 h): this command enables the host to set the number of sectors per track and the number of heads per cylinder. 9. read buffer (code: e4h): this command enables the host to read the current contents of the card ? s sector buffer.
2001-09-05 35/52 thncfxxxmaa series preliminar y version 1 0. read multiple (code: c4h): this command performs similarly to the read sectors command. interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a set multiple command. 11 . read long sector (code 22h or 23h): this command performs similarly to the read sector(s) command except that it returns 5 1 6 bytes of data instead of 5 1 2 bytes. 1 2. read sector(s) (code 20h, 2 1 h): this command reads from 1 to 256 sectors as specified in the sector count register. a sector count of 0 requests 256 sectors. the transfer beings specified in the sector number register. 1 3. read verify sector(s) (code: 40h or 4 1 h): this command is identical to the read sectors command, except that drq is never set and no data is transferred to the host. 1 4. recalibrate (code: 1 xh): this command is effectively a nop command to the card and is provided for compatibility purposes. 1 5. request sense (code: 03h): this command requests an extended error code after command ends with an error. 1 6. seek (code: 7xh): this command is effectively a nop command to the card although it does perform a range check. 1 7. set features (code: efh): this command is used by the host to establish or select certain features. feature feature feature feature operation operation operation operation 0 1 h enable 8-bit data transfers. 55h disable read look ahead. 66h disable power on reset (por) establishment of defaults at soft reset. 8 1 h disable 8-bit data transfers. bbh 4 bytes of data apply on read/write long commands. cch enable power on reset (por) establishment of defaults at soft reset. 1 8. set multiple mode (code: c6h): this command enables the card to perform read and write multiple operations and establishes the block count for these commands. 1 9. set sleep mode (code: e6h or 99h): this command causes the card to set bsy, enter the sleep mode, clear bsy and generate an interrupt. 20. stand by (code: e2h or 96h): this command causes the card to set bsy, enter the sleep mode (which corresponds to the ata ? standby ? mode), clear bsy and return the interrupt immediately. 2 1 . stand by immediate (code: e0h or 94h): this command causes the card to set bsy, enter the sleep mode (which corresponds to the ata ? standby ? mode), clear bsy and return the interrupt immediately. 22. translate sector (code: 87h): this command allows the host a method of determining the exact number of times a use sector has been erased and programmed.
2001-09-05 36/52 thncfxxxmaa series preliminar y version 23. wear level (code: f5h): this command effectively a nop command and only implemented for backward compatibility. the sector count register will always be returned with a 00h indicating wear level is not needed. 24. write buffer (code: e8h): this command enables the host to overwrite contents of the card ? s sector buffer with any data pattern desired. 25. write long sector (code: 32h or 33h): this command is provided for compatibility purposes and is similar to the write sector(s) command except that it writes 5 1 6 bytes instead of 5 1 2 bytes. 26. write multiple (code: c5h): this command is similar to the write sectors command. interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by set multiple command. 27. write multiple without erase (code: cdh): this command is similar to the write multiple command with the exception that an implied erase before write operation is not performed. 28. write sector(s): (code: 30h or 3 1 h): this command writes from 1 to 256 sectors as specified in the sector count register. a sector count of zero requests 256 sectors. the transfer begins at the sector specified in the sector number register. 29. write sector(s) without erase (code: 38h): this command is similar to the write sector(s) command with the exception that an implied erase before write operation is not performed. 30. write verify (code: 3ch): this command is similar to the write sector(s) command, except each sector is verified immediately after being written.
2001-09-05 37/52 thncfxxxmaa series preliminar y version sector transfer protocol sector transfer protocol sector transfer protocol sector transfer protocol 1 .sector read: sector read procedure after the card configured i/o interface is shown as follows. start i/o access, index= 1 set the cylinder low/high register set the head no. of drive head register ( 1 )set the logical sector number set the sector number register set in sector count register set ? 2 h ? in command register (2)set read sector command n read the status register n (3)polling until ready ? 5 1 h ? ? ? 58h ? ? y y read 256 times the data register (5 1 2 bytes) (4)burst data transfer error handle n (5)read more sectors? get all data? y wait the command input
2001-09-05 38/52 thncfxxxmaa series preliminar y version 2.sector write: write sector procedure after the card configured i/o interface is shown as follows. (1) (2) (3) (4) (5) 4h 5h 6h 3h 2h 7h 7h 7h 0h 0h 7h 7h 01h20h d0h 58h (data transfer) d0h 50h a0 to a10 -ce1 -ce2 -iow r -iord d0 to d15 -ireq
2001-09-05 39/52 thncfxxxmaa series preliminar y version start i/o access, index= 1 set the cylinder low/high register set the head no. of drive head register ( 1 )set the logical sector number set the sector number register set in sector count register set ? 30h ? in command register (2) n read the status register n (3) ? 5 1 h ? ? 58h ? ? y read 256 times the data register (5 1 2 bytes) (4)burst data transfer all data write n y n y read the status register n (5) ? 5 1 h ? ? 50h ? ? y y error handle wait the command input
2001-09-05 40/52 thncfxxxmaa series preliminar y version absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings parameter parameter parameter parameter symbol symbol symbol symbol value value value value unit unit unit unit note note note note all input/output voltages vin, vout -0.3 to v cc +0.3 v 1 v cc voltage v cc -0.3 to +6.7 v operation temperature range topr 0 to +85 c storage temperature range tstg -55 to + 1 25 c note: 1 . vin, vout min=-2.0 v for pulse width Q 20ns. recommended operation conditions recommended operation conditions recommended operation conditions recommended operation conditions parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit operation temperature ta 0 25 60 c 4.5 5.0 5.5 v v cc voltage v cc 3. 1 5 3.3 3.45 v capacitance (ta=25 capacitance (ta=25 capacitance (ta=25 capacitance (ta=25 c, f= 1 mhz) c, f= 1 mhz) c, f= 1 mhz) c, f= 1 mhz) parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit test conditions test conditions test conditions test conditions note note note note input capacitance cin 1 5 pf vin=0v 1 output capacitance count 1 5 pf vout=0v 1 note: 1 . this parameter is sampled and not 1 00% tested. (1) (2) (3) (4) (5) 4h 5h 6h 3h 2h 7h 7h 7h 0h 0h 7h 7h 01h30h d0h 58h (data transfer) d0h 50h a0 to a10 -ce1 -ce2 -iowr -iord d0 to d15 -ireq
2001-09-05 41/52 thncfxxxmaa series preliminar y version card system performance card system performance card system performance card system performance item item item item performance performance performance performance set up times (reset to ready) 500 ms (max) set up times (sleep to idle) 1 00 s (max) set up times (deep power down to idle) 4 ms (max) data transfer rate to/from host 1 6 mbyte/s burst (max), theoretically sustained read transfer rate 5.4mbyte/s (max), actually sustained write transfer rate 3.2mbyte/s (max), actually controller overhead (command to drq) 4 ms (max) data transfer cycle end to ready(sector write) 500 s (typ), 50 ms (max)
2001-09-05 42/52 thncfxxxmaa series preliminar y version dc characteristics dc characteristics dc characteristics dc characteristics- - - - 1 (ta=0 to +70 c, v 1 (ta=0 to +70 c, v 1 (ta=0 to +70 c, v 1 (ta=0 to +70 c, v cc cc cc cc = 3.3v 5%, 5v 1 0%) = 3.3v 5%, 5v 1 0%) = 3.3v 5%, 5v 1 0%) = 3.3v 5%, 5v 1 0%) paramet paramet paramet parameter er er er symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit test conditions test conditions test conditions test conditions input voltage v ih 2.0 v cc +0.3 v v il -0.3 0.6 v schmitt circuit v t+ 2. 1 v v cc =3.3v v t- 1 .2 v output voltage (4ma) v oh 2.4 v i oh =-4ma v ol 0.4 v i ol =4ma input leakage current i li 1 a output leakage current i lo 1 a v out =high impedance pull-up current (resistivity) i pu 20/( 1 65) 45/(73) 72/(45) a(k )v force =3.3v pull-down current (resistivity) i pd -20/( 1 800) -48/(206) -72/(85) a(k )v force =0v sleep/standby current i sp 1 (0.2) (0.5) ma cmos level (control signal=v cc -0.2) sector read current i ccr (dc) (25) (50) ma cmos level (control signal=v cc -0.2) i ccr (peak) (50) (80) ma sector write current i ccw (dc) (25) (50) ma cmos level (control signal=v cc -0.2) i ccw (peak) (50) (80) ma symbol symbol symbol symbol parameter parameter parameter parameter min min min min max max max max tclkl clock low time 20 tclkh clock high time 20 xin t clkl t clkh
2001-09-05 43/52 thncfxxxmaa series preliminar y version ac characteristics (ta=0 to + ac characteristics (ta=0 to + ac characteristics (ta=0 to + ac characteristics (ta=0 to +6 6 6 60 0 0 0 c, v c, v c, v c, v cc cc cc cc = 5v = 5v = 5v = 5v 1 0%, v 1 0%, v 1 0%, v 1 0%, v cc cc cc cc = 3.3v = 3.3v = 3.3v = 3.3v 5%) 5%) 5%) 5%) attribute memory read ac characteristics attribute memory read ac characteristics attribute memory read ac characteristics attribute memory read ac characteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit read cycle time tcr 1 00 ns address access time ta(a) 1 00 ns -ce access time ta(ce) 1 00 ns -oe access time ta(oe) 50 ns output disable time(-ce) tdis(ce) 40 ns output disable time(-oe) tdis(oe) 40 ns output enable time(-ce) ten(ce) 5 ns output enable time(-oe) ten(oe) 5 ns data valid time(a) tv(a) 0 ns address setup time tsu(a) 30 ns attribute memory read timing attribute memory read timing attribute memory read timing attribute memory read timing an tc ( r ) -reg -ce -oe dout ta ( a ) tsu ( a ) ta ( ce ) ta ( oe ) ten ( oe ) ten ( ce ) tv ( a ) tdls ( ce ) tdls ( oe )
2001-09-05 44/52 thncfxxxmaa series preliminar y version attribute memory write ac characteristics attribute memory write ac characteristics attribute memory write ac characteristics attribute memory write ac characteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit write cycle time tcw 1 00 ns write pulse time tw(we) 60 ns address setup time tsu(a) 30 ns data setup time (-we) tsu(d-weh) 40 ns data hold time th(d) 30 ns write recover time trec(we) 20 ns attribute memory write timing attribute memory write timing attribute memory write timing attribute memory write timing an -reg -we -ce din data in valid tc ( w ) -oe tsu(a) tsu(a) tsu(a) tsu(a) trec ( we ) tw ( we ) tsu ( d-weh ) th ( d )
2001-09-05 45/52 thncfxxxmaa series preliminar y version i/o access read ac characteristics i/o access read ac characteristics i/o access read ac characteristics i/o access read ac characteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit data delay after ? iord td(iord) 45 ns data hold following ? iord th(iord) 0 ns -iord pulse width tw(iord) 80 ns address setup before -iord tsua(iord) 30 ns address hold following ? iord tha(iord) 20 ns -ce setup before ? iord tsuce(iord) 0 ns -ce hold following ? iord thce(iord) 0 ns -reg setup before ? iord tsureg(iord) 0 ns -reg hold following ? iord threg(iord) 0 ns -inpack delay failing from ? iord tdfinpack(iord) 0 45 ns -inpack delay rising from ? iord tdrinpack(iord) 45 ns -iois 1 6 delay falling from address tdfiois 1 6(adr) 35 ns -iois 1 6 delay rising from address tdriois 1 6(adr) 35 ns i/o access read timing i/o access read timing i/o access read timing i/o access read timing+ + + + tsua(iord) tsureg(iord) tsuce(iord) tw(iord) threg(iord) thce(iord) tha(iord) tdfinpack(iord) an -reg -ce -iord -inpack -iois16 dout tdfiois16(adr) td(iord) tdninpack(iord) tdniois16(adr)
2001-09-05 46/52 thncfxxxmaa series preliminar y version i/o access write ac characteristics i/o access write ac characteristics i/o access write ac characteristics i/o access write ac characteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit data setup before ? iowr tsu(iowr) 40 ns data hold following ? iowr th(iowr) 30 ns -iowr pulse width tw(iowr) 80 ns address setup before ? iowr tsua(iowr) 30 ns address hold following ? iowr tha(iowr) 20 ns -ce setup before ? iowr tsuce(iowr) 0 ns -ce hold following ? iowr thce(iowr) 0 ns -reg setup before ? iowr tsureg(iowr) 0 ns -reg hold following ? iowr threg(iowr) 0 ns -iois 1 6 delay falling from address tdfiois 1 6(adr) 35 ns -iois 1 6 delay rising from address tdriois 1 6(adr) 35 ns i/o access write timing i/o access write timing i/o access write timing i/o access write timing tsu a (iowr) tsuce(iowr) tw(iowr) threg(iowr) thce(iowr) tha(iowr) an -reg -ce -iowr -iois16 din tdfiois16(adr) tsu(iowr) tdriois16(adr) tsureg(iowr) din valid th(iowr)
2001-09-05 47/52 thncfxxxmaa series preliminar y version command memory access read ac characteristics command memory access read ac characteristics command memory access read ac characteristics command memory access read ac characteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit -oe access time ta(oe) 60 ns output disable time (-oe) tdis(oe) 40 ns address setup time tsu(a) 30 ns address hold time th(a) 20 ns -ce setup time tsu(ce) 0 ns -ce hold time th(ce) 0 ns common memory access read timing common memory access read timing common memory access read timing common memory access read timing tsu(a) th(a) an -reg -ce -oe dout tsu(ce) ta(oe) th(ce) tdis(oe)
2001-09-05 48/52 thncfxxxmaa series preliminar y version common memory access write ac characteristic common memory access write ac characteristic common memory access write ac characteristic common memory access write ac characteristic paramete paramete paramete parameter r r r symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit data setup time (-we) tsu(d-weh) 40 ns data hold time th(d) 30 ns write pulse time tw(we) 80 ns address setup time tsu(a) 30 ns -ce setup time tsu(ce) 0 ns write recover time trec(we) 20 ns -ce hold following -we th(ce) 0 ns common memory access write timing common memory access write timing common memory access write timing common memory access write timing tsu(a) th(a) an -reg -ce -we din tsu(ce) tw(we) th(ce) th(d) trec(we) din valid
2001-09-05 49/52 thncfxxxmaa series preliminar y version the ide mode access read ac characteristics the ide mode access read ac characteristics the ide mode access read ac characteristics the ide mode access read ac characteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit data delay after iord td(iord) 45 ns data hold following iord th(iord) 0 ns iord with time tw(iord) 80 ns address setup before iord tsua(iord) 30 ns address hold following iord tha(iord) 20 ns ce setup before iord tsuce(iord) 0 ns ce hold following iord thce(iord) 0 ns iois 1 6 delay falling from address tdfiois 1 6(adr) 35 ns iois 1 6 delay rising from address tsfiois 1 6(adr) 35 ns true ide mode access read timing true ide mode access read timing true ide mode access read timing true ide mode access read timing an -iois16 dout -ce -iord tsua(iord) tsuce(iord) tw(iord) td(iord) tdfiois16(adr) tha(iord) thce(iord) tdriois16(adr) th(iord)
2001-09-05 50/52 thncfxxxmaa series preliminar y version true ide mode access write ac cha true ide mode access write ac cha true ide mode access write ac cha true ide mode access write ac characteristics racteristics racteristics racteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit data setup before iowr tsu(iowr) 40 ns data hold following iowr th(iowr) 30 ns iord width time tw(iowr) 80 ns address setup before iowr tsua(iowr) 30 ns address hold following iowr tha(iowr) 20 ns ce setup before iowr tsuce(iowr) 0 ns ce hold following iowr thce(iowr) 0 ns iois 1 6 delay falling from address tdfiois 1 6(adr) 35 ns iois 1 6 delay rising from address tsfiois 1 6(adr) 35 ns true ide mode access write timing true ide mode access write timing true ide mode access write timing true ide mode access write timing an -iois16 dout -ce -iord tsua(iowr) tsuce(iowr) tw(iowr) tdfiois16(adr) tha(iowr) thce(iowr) tdriois16(adr) th(iowr) din valid tsu(iowr)
2001-09-05 51/52 thncfxxxmaa series preliminar y version reset characteristics (only memory card mode or i/o card mode) reset characteristics (only memory card mode or i/o card mode) reset characteristics (only memory card mode or i/o card mode) reset characteristics (only memory card mode or i/o card mode) hard reset characteristics hard reset characteristics hard reset characteristics hard reset characteristics parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit test test test test conditions conditions conditions conditions reset setup time tsu(reset) 1 00 ms -ce recover time trec(vcc) 1 s vcc rising up time tpr 0. 1 1 00 ms vcc falling down time tpf 3 300 ms reset pulse width tw(reset) 1 0 s th(hi-zreset) 1 ms ts(hi-zreset) 0 ms hard reset timing hard reset timing hard reset timing hard reset timing vcc -ce1, -ce2 reset high-z th(hi-zreset) tsu(reset) tw(reset) low 90% 10% tpr ts(hi-zreset) high-z 90% tpr 10% trec(vcc)
2001-09-05 52/52 thncfxxxmaa series preliminar y version power on reset characteristics power on reset characteristics power on reset characteristics power on reset characteristics power on reset sequence must need by ? porst at the rising of v cc . parameter parameter parameter parameter symbol symbol symbol symbol min min min min typ typ typ typ max max max max unit unit unit unit test test test test conditions conditions conditions conditions -ce setup time tsu(vcc) 1 00 ms vcc rising up time tpr 0. 1 1 00 ms power on reset timing power on reset timing power on reset timing power on reset timing attention for card use attention for card use attention for card use attention for card use in the reset or power off, the information of all registers is cleared. notice that the card insertion/removal should not be executed during host is active, if the card is used in true ide mode. after the card hard reset, soft reset, or power on reset, ata reset, command applied the card cannot access during +rdy/-bsy pin is ? low ? level. flash card can ? t be operated in this case. before the card insertion v cc can not be supplied to the card. after confirmation that ? cd 1 , -cd2 pins are inserted, supply v cc to the card. note: -oe must be kept at the v cc level during power on reset in memory card mode and i/o card mode. ? oe must be kept constantly at the gnd level in true ide mode. tpr vcc -porst -ce1, -ce2 tsu(vcc)

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